Thin film transistor array panel and method for fabricating the same

ABSTRACT

The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on the insulating substrate. The gate wire includes a gate line and a gate pad connected to one end of the gate line. A gate insulating layer is formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad. A semiconductor pattern is formed on the gate insulating layer. A data wire is formed on the gate insulating layer. The data wire includes a data line, a source electrode connected to the data line, a drain electrode facing the source electrode and a data pad connected to one end of the data line. A passivation layer is formed on the gate insulating layer while exposing the data pad and a portion of the data line close to the data pad.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array panel anda fabricating method thereof and, more particularly, to a thin filmtransistor array panel for a liquid crystal display and a fabricatingmethod thereof.

(b) Description of the Related Art

Currently, an LCD is one of the most widely used flat panel displays. AnLCD, which includes two panels having electrodes and a liquid crystallayer interposed therebetween, controls the transmittance of lightpassing through the liquid crystal layer by re-arranging liquid crystalmolecules in the liquid crystal layer with voltages applied to theelectrodes.

One of the LCDs for improving viewing angle provides one of the twopanels with linear electrodes parallel to each other and thin filmtransistors (“TFTs”) for switching the voltages applied to theelectrodes to re-arrange the liquid crystal molecules, which areinitially aligned parallel to the panels.

The panel with the TFTs (referred to as the “TFT array panel”hereinafter) is usually fabricated by photo etch using several masks.Although the number of the currently used masks is five or six, it isrequired to decrease the number in order to reduce the production cost.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a TFT array paneland a fabricating method thereof, which involves simplified processingsteps.

This and other objects may be achieved by forming a gate insulatinglayer or a passivation layer made of an organic insulating material byway of printing technique or slit-coating technique.

In detail, an inventive TFT array panel includes: an insulatingsubstrate; a gate wire formed on the insulating substrate and includinga gate line, and a gate pad connected to one end of the gate line; agate insulating layer formed on the insulating substrate while exposingthe gate pad and a portion of the gate line close to the gate pad; asemiconductor pattern formed on the gate insulating layer; a data wireformed on the gate insulating layer and including a data lineintersecting the gate line, a source electrode connected to the dataline and contacting the semiconductor pattern, a drain electrode facingthe source electrodes and contacting the semiconductor pattern, and adata pad connected to one end of the data line; and a passivation layerformed on the gate insulating layer while exposing the data pad and aportion of the data line close to the data pad.

The TFT array panel may further include a common wire formed on thesubstrate and including a common electrode line parallel to the gateline, a common electrode connected to the common electrode line, and acommon electrode pad connected to one end of the common electrode line,and the gate insulating layer preferably exposes the common electrodepad, and a portion of the common electrode line close to the commonelectrode pad. The gate insulating layer or the passivation layer ispreferably made of an organic insulating material.

An inventive method of fabricating a TFT array panel includes: forming agate wire on an insulating substrate, the gate wire including a gateline, and a gate pad connected to one end of the gate line; forming agate insulating layer made of an organic insulating material on theinsulating substrate such that the gate insulating layer exposes thegate pad and a portion of the gate line close to the gate pad; forming asemiconductor pattern on the gate insulating layer; forming a data wireon the gate insulating layer, the data wire having a data lineintersecting the gate line, a source electrode connected to the dataline and contacting the semiconductor pattern, a drain electrode facingthe source electrode and contacting the semiconductor pattern, and adata pad connected to one end of the data line; and forming apassivation layer made of an organic insulating material on the gateinsulating layer such that the passivation layer exposes the data padand a portion of the data line close to the data pad. The formation ofat least one of the gate insulating layer and the passivation layer ismade by way of slit coating or printing.

The gate insulating layer may be surface-flattened after the formationof the gate insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout view of a TFT array panel according to an embodimentof the present invention;

FIG. 2 is a sectional view taken along the line II-II′ shown in FIG. 1;

FIG. 3A is a layout view of a TFT array panel in the first step offabricating method thereof;

FIG. 3B is a sectional view taken along the line IIIb-IIIb′ shown inFIG. 3A;

FIG. 4A is a layout view of a TFT array panel in the step following FIG.3A;

FIG. 4B is a sectional view taken along the line IVb-IVb′ shown in FIG.4A;

FIG. 5A is a layout view of a TFT array panel in the step following FIG.4A;

FIG. 5B is a sectional view taken along the line Vb-Vb′ shown in FIG.5A;

FIGS. 6 to 9 sequentially illustrate the intermediate steps offabricating the TFT array panel with a cross section shown FIG. 5B fromthe TFT array panel with a cross section shown in FIG. 4B;

FIG. 10 illustrates a gate insulating pattern made by the steps offabricating a TFT array panel according to an embodiment of the presentinvention; and

FIG. 11 illustrates a passivation layer pattern made by the steps offabricating a TFT array panel according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Now, methods of manufacturing a TFT array panel according to embodimentsof the present invention will be described with reference to theaccompanying drawings.

Hereinafter, the present invention will be described by way of anexemplary TFT array panel for an LCD driving liquid crystal usinghorizontal electric field for wide viewing angle.

FIG. 1 is a layout view of a TFT array panel according to an embodimentof the present invention, and FIG. 2 is a sectional view of the TFTarray panel shown in FIG. 1 taken along the line II-II′.

As shown in FIGS. 1 and 2, a gate wire 22, 24 and 26 and a common wire27 and 28 are formed on an insulating substrate 10. The gate wire 22, 24and 26 includes a plurality of gate lines 22 extending in a transversedirection, a plurality of gate pads 24 connected to one ends of the gatelines 22 to transmit scanning signals thereto, and a plurality of gateelectrodes 26 connected to the gate lines 22. The common wire 27 and 28includes a plurality of common electrode lines 27 parallel to the gatelines 22 and transmitting common electrode signals (referred to as“common signals” hereinafter) from an external device, and a pluralityof common electrodes 28 connected to the common electrode lines 27 andextending in a longitudinal direction.

It is preferable that the gate wire 22, 24 and 26 and the common wire 27and 28 are made of a low resistivity metallic material. The gate wire22, 24 and 26 and the common wire 27 and 28 have either a single-layeredstructure or a multiple-layered structure. The single-layered structurepreferably includes Cr, Cr alloy, Mo, Mo alloy, Al, Al alloy, Ag, or Agalloy. The double-layered structure includes one layer preferably madeof a low resistivity metallic material, and the other layer preferablymade of a material bearing a good contact characteristic with othermaterials.

A gate insulating layer 30 preferably made of an organic insulatingmaterial is formed on the insulating substrate 10. The gate insulatinglayer 30 covers the entire surface of the panel except for the gate pads24. That is, the gate insulating layer 30 covers the gate lines 22, thegate electrodes 26 and the common wire 27 and 28, while exposing thegate pads 24.

The dotted line indicated by the reference numeral 31 in FIG. 1 refersto the peripheral boundaries of the gate insulating layer 30. It ispreferable that the gate insulating layer 30 is made of a low dielectricmaterial exhibiting excellent flattening characteristic, such asbisbenzocyclobutene (BCB) and perfluorocyclobutene (PFCB).

A semiconductor pattern 42 preferably made of amorphous silicon isformed on the gate insulating layer 30, and an ohmic contact layerpattern 55 and 56 preferably made of amorphous silicon doped withimpurity are formed on the semiconductor pattern 42.

A data wire 62, 64, 65 and 66 and a pixel wire 67 and 68 connectedthereto are formed on the ohmic contact layer pattern 55 and 56. Thedata wire 62, 64, 65 and 66 and the pixel wire 67 and 68 are preferablymade of a low resistivity metallic material bearing good contact withsemiconductor. The data wire 62, 64, 65 and 66 includes a plurality ofdata lines 62 intersecting the gate lines 22 and extending in thelongitudinal direction, a plurality of data pads 64 connected to oneends of the data lines 62 for receiving data signals from an externaldevice to transmit to the data lines 62, a plurality of sourceelectrodes 65 protruded from the data lines 62, and a plurality of drainelectrodes 66 opposite the source electrodes 65. The pixel wire 67 and68 includes a plurality of pixel electrode lines 67 connected to thedrain electrodes 66 and extending parallel to the gate lines 22, and aplurality of pixel electrodes 68 connected to the pixel electrode lines67 and extending in the longitudinal direction. The pixel electrodes 68and the common electrodes 28 are arranged in an alternate manner.

Under the application of different voltages, the common wire 27 and 28and the pixel wire 67 and 68, which are aligned parallel to each otheron the insulating substrate 10, generate horizontal electric fieldtherebetween. The driving of liquid crystal with the horizontal electricfield realizes a wide viewing angle.

It is preferable that the data wire 62, 64, 65 and 66 and the pixel wire67 and 68 are made of a low resistivity metallic material. Like the gatewire 22, 24 and 26, the data wire 62, 64, 65 and 66 has either asingle-layered structure or a double-layered structure. Thesingle-layered structure preferably includes Cr, Cr alloy, Mo, Mo alloy,Al, Al alloy, Ag, or Ag alloy. The double-layered structure includes onelayer preferably made of a low resistivity metallic material, and theother layer preferably made of a material bearing a good contactcharacteristic with other materials.

The gate electrodes 26, the source electrodes 65, the drain electrodes66, and portions of the semiconductor pattern 42 between the source andthe drain electrodes 65 and 66 form TFTs.

The semiconductor pattern 42 has substantially the same planar shape asthe data wire 62, 64, 65 and 66 and the pixel wire 67 and 68 except forthe channel areas of the TFTs, i.e., the areas between the source andthe drain electrodes 65 and 66. In detail, the semiconductor pattern 42has the same planar shape as a pattern including the data lines 62, thedata pads 64, the source electrodes 65, the drain electrodes 66, thepixel electrode lines 67 and the pixel electrodes 68 except that thesemiconductor pattern 42 further includes portions defined as TFTchannels located between the source and the drain electrodes 65 and 66.

The ohmic contact layer pattern 55 and 56 have a role of reducing thecontact resistance between the underlying semiconductor pattern 42 andthe overlying data wire 62, 64, 65 and 66 and pixel wire 67 and 68, andhas the same planar shape as a pattern including the data wire 62, 64,65 and 66 and the pixel wire 67 and 68. One portion 55 of the ohmiccontact layer pattern 55 and 56 contacts the data line 62, the data pad64 and the source electrode 65, which are integrated into one body. Theother portion 56 of the ohmic contact layer pattern 55 and 56 contactsthe drain electrode 66, the pixel electrode line 67 and the pixelelectrode 68, which are also integrated into one body.

A passivation layer 70 preferably made of an organic insulating materialis formed on the gate insulating layer 30. The passivation layer 70covers the entire surface of the panel except for the gate pads 24 andthe data pads 64. That is, the passivation layer 70 covers the datalines 62, the source electrodes 65, the drain electrodes 66, the pixelelectrode lines 67, and the pixel electrodes 68. Therefore, the gatepads 24 and the data pads 64 are not covered by the passivation layer 70to be exposed.

The dotted line indicated by the reference numeral 71 in FIG. 1 refersto the peripheral boundaries of the passivation layer 70. It ispreferable that the gate insulating layer 30 is made of a low dielectricmaterial exhibiting excellent flattening characteristic, such as BCB andPFCB.

As described above, the TFT array panel according to an embodiment ofthe present invention interposes an organic insulating layer having arelatively large thickness between the data lines and the gate lines toreduce the parasitic capacitance therebetween. Furthermore, theembodiment of the present invention gives an advantage that as wideviewing angle can be realized by driving the liquid crystal withhorizontal electric field generated between the common electrode and thepixel electrode.

Now, a method of fabricating a TFT array panel according to anembodiment of the present invention will be now described in detail withreference to FIGS. 3A to 9 as well as FIGS. 1 and 2.

First, as shown in FIGS. 3A and 3B, a layer based on Cr, Cr alloy, Mo,Mo alloy, Al, Al alloy, Ag ox Ag alloy is deposited on an insulatingsubstrate 10, and patterned by photo etch using a mask to form a gatewire 22, 24 and 26 including a plurality of gate lines 22, a pluralityof gate pads 24 and a plurality of gate electrodes 26, and a common wire27 and 28 including a plurality of common electrode lines 27 and aplurality of common electrodes 28.

Thereafter, as shown in FIGS. 4A and 4B, a low dielectric organicinsulating material such as BCB and PFCB is coated on the insulatingsubstrate 10 provided with the gate wire 22, 24 and 26 and the commonwire 27 and 28 by way of printing or slit coating, thereby forming agate insulating layer 30. The gate insulating layer 30 may be planarizedby way of grinding to improve the deposition and contact characteristicsof the layers to be formed later. The slit coating utilizes a slitcoater that coats an organic insulating material on the substrate 10 byspraying the organic insulating material with the frontal end of a slitnozzle with slit width of 0.1 mm or less.

The print of the organic insulating material on the substrate 10 isperformed such that the gate insulating layer 30 does not cover the gatepads 24.

The dotted line indicated by the reference numeral 31 refers to theperipheral boundaries of the gate insulating layer 30.

As shown in FIGS. 5A and 5B, a semiconductor layer, an impurities-dopedsemiconductor layer and a metallic layer are sequentially deposited onthe gate insulating layer 30, and patterned by photo etch to form asemiconductor pattern 42, an ohmic contact layer pattern 55 and 56, anda metallic pattern including a data wire 62, 64, 65 and 66 and a pixelwire 67 and 68.

The data wire 62, 64, 65 and 66 and the pixel wire 67 and 68 contact theohmic contact layer pattern 55 and 56 located thereunder and having thesame planar shape thereas, and the ohmic contact layer pattern 55 and 56contacts the semiconductor pattern 42 placed thereunder. Thesemiconductor pattern 42 has substantially the same planar shape as thedata wire 62, 64, 65 and 66 but further includes areas defined as TFTchannels located between the source and the drain electrodes 65 and 66.

The data wire 62, 64, 65 and 66, the ohmic contact layer pattern 55 and56 and the semiconductor pattern 42 is alternatively formed using onlyone mask. This will be now described with reference to FIGS. 6 to 9.

First, as shown in FIG. 6, a semiconductor layer 40 and a dopedsemiconductor layer 50 are sequentially deposited on the gate insulatinglayer 30 by chemical vapor deposition (“CVD”). Subsequently, a metallayer 60 made of Cr, Cr alloy, Mo, Mo alloy, Al, Al alloy, Ag, or Agalloy is deposited by sputtering.

Next, after a photoresist film is coated on the metal layer 60 andexposed to light through a mask (not shown), the photoresist film isdeveloped to obtain a photoresist pattern 112 and 114. The obtainedphotoresist pattern 112 and 114 is such that first portions 112 locatedon areas A for data wire and pixel wire (hereinafter referred to as“data areas” hereinafter) is thicker than second portions 114 located onchannel areas B of TFTs between source and drain electrodes 65 and 66and there is no residue on the remaining areas C. The thickness ratio ofthe second portions 114 to the first portions 112 is adjusted dependingupon the etching conditions in the etching steps to be described later.It is preferable that the thickness of the second portions 114 is equalto or less than half of the thickness of the first portions 112.

The position-dependent thickness of the photoresist film is obtained byusing a mask with position-dependent transmissivity. In order to adjustthe amount of light exposure, a slit pattern, a lattice pattern ortranslucent films are provided on a mask. When using a slit pattern, itis preferable that the width of the portions between the slits or thedistance between the portions, i.e., the width of the slits is smallerthan the resolution of an exposer used for the photolithography. In caseof using translucent films, thin films with different transmittances orwith different thicknesses may be used to adjust the transmittance ofthe mask.

When the photoresistive film is irradiated with light through such amask, polymers of the portions on the areas C directly exposed to thelight are almost completely decomposed, and those of the portions on theareas B facing the slit pattern or the translucent films are notcompletely decomposed due to the small amount of light exposure. Thepolymers of the portions on the areas A blocked by light-blocking filmsare hardly decomposed. Here, it is required not to make the exposuretime long enough to decompose all the molecules.

Development of the photoresistive film selectively exposed to lightmakes the portions having the polymers, which are not decomposed, to beleft, and makes the middle portions exposed to the smaller lightirradiation to be thinner than the portions which do not experience thelight exposure.

Subsequently, as shown in FIG. 7, the exposed portions of the metallayer 60 on the areas C are removed to expose the underlying portions ofthe doped semiconductor layer 50. Consequently, a metal pattern 61 onthe channel areas B and the data areas A are left over, while portionsof the metal layer 60 on the remaining areas C is removed out to exposethe underlying portions of the doped semiconductor layer 50. Theobtained metal pattern 61 is such that the source and the drainelectrodes 65 and 66 are still connected without separation toincorporate the data wire and the pixel wire.

Next, as shown in FIG. 8, the exposed portions of the dopedsemiconductor layer 50 on the remaining areas C and the underlyingportions of the semiconductor layer 40 are simultaneously removed by dryetching together with the second portions 114. The etch is preferablymade under a condition that the photoresist pattern 112 and 114, thedoped semiconductor layer 50 and the semiconductor layer 40 aresimultaneously etched while the gate insulating layer 30 is not etched.Particularly, the etching ratios of the photoresist pattern 112 and 114and the semiconductor layer 40 are preferably equal to each other. Forexample, a gas mixture of SF₆ and HCl or a gas mixture of SF₆ and O₂etches the two layers to almost the same thickness.

For the equal etching ratios of the photoresist pattern 112 and 114 andthe semiconductor layer 40, the thickness of the second photoresistportions 114 is preferably equal to or less than the sum of thethicknesses of the semiconductor layer 40 and the doped semiconductorlayer 50.

In this way, the second photoresist portions 114 placed on the channelareas B are removed to expose the conductive pattern 61, and theportions of the doped semiconductor layer 50 and the semiconductor layer40 on the remaining area C are removed to expose the underlying gateinsulating layer 30. Meanwhile, the first photoresist pattern portions112 on the data areas A are also etched to have reduced thickness.

In this step, the formation of a semiconductor pattern 42 is completed,and the ohmic contact layer pattern 52 with the same planar shape withthe semiconductor pattern 42 is formed thereon.

Residue of the second photoresist portions 144 remained on the surfaceof the metal pattern 61 on the channel areas B is then removed byashing.

Subsequently, as shown in FIG. 9, the portions of the metal pattern 61on the channel areas B and the underlying portions of the ohmic contactlayer pattern 52 are etched using the remained second photoresistportions 112 as a mask. At this time, top portions of the semiconductorpattern 42 may be removed to cause thickness reduction, and the firstphotoresist portions 112 are etched to a predetermined thickness. Theetching is performed under the condition that the gate insulating layer30 is hardly etched, and it is preferable that the photoresist patternis so thick to prevent the second photoresist portion 112 from beingetched to expose the underlying metal pattern.

In this way, the source and the drain electrodes 65 and 66 in the metalpattern 61 are separated from each other. On the one hand, the data line62, the data pad 64 and the source electrode 65 are formed withintegrated into one body, and on the other, the drain electrode 66, thepixel electrode line 67 and the pixel electrode 68 are formed withintegrated into one body. The formation of the underlying ohmic contactlayer pattern 55 and 56 is also completed.

Removal of the remaining first photoresist pattern portion 112 completesa panel having a cross section shown in FIG. 5B.

Thereafter, as shown in FIGS. 1 and 2, a low dielectric organicinsulating material such as BCB and PFCB is coated on the panel providedwith the data wire 62, 64, 65 and 66 and the pixel wire 67 and 68 by wayof printing or slit coating, thereby forming a passivation layer 70. Inorder to prevent the passivation layer 70 from being formed on the gatepads 24 and the data pads 64, the printing plate is designed or the slitcoating nozzle is controlled such that the passivation layer 70 does notcover the gate pads 24 and the data pads 64.

Since the TFT array panel manufactured by a method according to anembodiment of the present invention entirely exposes the gate and thedata pads 24 and 64, it is not necessary to introduce subsidiary gateand data pads for reinforcing the contacts of the gate and the data pads24 and 64 to external driving ICs.

The above-described inventive TFT array panel may include a commonsignal line electrically interconnecting a plurality of common electrodelines, and a common signal pad connected to the common signal line. Thiswill be now described in detail with reference to FIGS. 10 and 11.

FIG. 10 illustrates a gate insulating pattern formed by the steps offabricating a TFT array panel according to an embodiment of the presentinvention, and FIG. 11 illustrates a passivation layer pattern formed bythe steps of fabricating a TFT array panel according to an embodiment ofthe present invention.

A plurality of gate lines 22 with a plurality of gate pads 24 connectedto the one ends of the gate lines 22 and a plurality of common electrodelines 27 interposed between the gate lines 22 are provided on ainventive TFT array panel. The respective common electrode lines 27 areelectrically connected to each other via a common line 38 extending inthe longitudinal direction. A common electrode pad 39 for receivingcommon signals from an external device and transmit to the common signalline is provided at one end of the common signal line 38.

The gate insulating layer 30 is printed or coated on the panel 100 suchthat the gate pads 24 and the common electrode pad 39 are exposed asshown in FIG. 10.

Furthermore, a passivation layer 70 is printed or slit-coated on thepanel 200 further provided by subsequent processes with the data wire62, 64, 65 and 66 including a plurality of data lines 62 intersectingthe gate lines 22 and a plurality of data pads 24 formed at one ends ofthe data lines 62 such that the data pads 64 as well as the gate pads 24and the common electrode pads 39 added in the later processes areexposed as shown in FIG. 11.

In the inventive method of fabricating a TFT array panel, with the useof a printing technique or a slit coating technique, the pad areas arenot covered by the gate insulating layer and the passivation layer to beexposed. This omits the step of forming contact holes at the gateinsulating layer or the passivation layer to expose the pads.

The present invention prints or slit-coats a gate insulating layer and apassivation layer made of an organic insulating material such that gatepads and data pads are exposed, thereby simplifying a method offabricating a TFT array panel, for example, reducing the number ofmasks.

1. A thin film transistor array panel comprising: an insulatingsubstrate; a gate wire formed on the insulating substrate and includinga gate line, and a gate pad connected to one end of the gate line; agate insulating layer formed on the insulating substrate while exposingthe gate pad and a portion of the gate line close to the gate pad; asemiconductor pattern formed on the gate insulating layer; a data wireformed on the gate insulating layer and including a data lineintersecting the gate line, a source electrode projecting from the dataline and contacting the semiconductor pattern, a drain electrode facingthe source electrodes and contacting the semiconductor pattern, and adata pad connected to one end of the data line; and a passivation layerformed on the gate insulating layer while exposing the data pad and aportion-of the data line close to the data pad, wherein the passivationlayer further exposes a portion of the gate insulating layer formedclose to the gate pad, and wherein the passivation layer comprisesorganic material.
 2. The thin film transistor array panel of claim 1further comprising a common wire formed on the substrate and including acommon electrode line parallel to the gate line, a common electrodeconnected to the common electrode line, and a common electrode padconnected to one end of the common electrode line, the gate insulatinglayer exposing the common electrode pad, and a portion of the commonelectrode line close to the common electrode pad.
 3. The thin filmtransistor array panel of claim 1 or 2 wherein at least one of the gateinsulating layer and the passivation layer is made of an organicinsulating material.
 4. The thin film transistor array panel of claim 1wherein the semiconductor pattern having a thin portion disposed betweenthe source electrode and the drain electrode, the thin portion beingthinner than a portion of the semiconductor pattern contacting thesource electrode and the drain electrode.
 5. The thin film transistorarray panel of claim 1 further comprising a pixel electrode linedisposed substantially parallel to the gate line and connected to thedrain electrode formed on the substrate, wherein the drain electrode isa projection from the pixel electrode line and is disposed substantiallyparallel to the gate line.
 6. A thin film transistor array panelcomprising: an insulating substrate; a gate wire formed on theinsulating substrate and including a gate line, and a gate pad connectedto one end of the gate line; a gate insulating layer formed on theinsulating substrate while exposing the gate pad and a portion of thegate line close to the gate pad; a semiconductor pattern formed on thegate insulating layer; a data wire formed on the gate insulating layerand including a data line intersecting the gate line, a source electrodeconnected to the data line and contacting the semiconductor pattern, adrain electrode facing the source electrodes and contacting thesemiconductor pattern, and a data pad connected to one end of the dataline; a common wire formed on the substrate and including a commonelectrode line parallel to the gate line, a common electrode connectedto the common electrode line, and a common electrode pad connected toone end of the common electrode line, the gate insulating layer exposingthe common electrode pad, and a portion of the common electrode lineclose to the common electrode pad; and a passivation layer formed on thegate insulating layer while exposing the data pad and a portion of thedata line close to the data pad wherein the passivation layer furtherexposes a portion of the gate insulating layer and an end portion of thecommon electrode line close to the gate pad.
 7. The thin film transistorarray panel of claim 6 further comprising a pixel electrode linedisposed substantially parallel to the gate line and connected to thedrain electrode formed on the substrate, wherein the drain electrode isa projection from the pixel electrode line and is disposed substantiallyparallel to the gate line.